Semi-flattened pin optimization process for hierarchical physical designs
US7469399B2 · kind B2 · utility
2Cited by
5References
1Claims
0Family size
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Key dates
| Filing date | Sep 13, 2006 |
| Grant date | Dec 23, 2008 |
| Priority date | — |
| Expiry date | Mar 5, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.