Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention
US7470616B1 · kind B1 · utility
16Cited by
6References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2008 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | May 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating metal wiring layers of a semiconductor device are provided where damascene interconnect structures are formed in a BEOL process that incorporates a dielectric cap-open-first process to achieve hard mask retention and to control the gouging of a buffer oxide layer to prevent exposure of underlying features protected by the buffer oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.