Wirebond pad for semiconductor chip or wafer
US7470997B2 · kind B2 · utility
47Cited by
14References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2004 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Mar 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and connected via the metal caps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.