Multiplexer circuit
US7471135B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2006 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Dec 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplexer circuit provided herein includes a plurality of pass devices coupled in parallel between a power supply and a ground supply. According to one embodiment, each pass device may include a first pair of transistors, which is coupled in series between the power supply and the ground supply, and a second pair of transistors, which is coupled to the first pair of transistors for controlling a current passed there through. In general, the second pair of transistors may be configured for increasing the amount of current passed through the first pair of transistors. For example, the second pair of transistors may utilize a bootstrapping effect to increase a pair of control voltages supplied to the gate terminals of the first pair of transistors. The increased control voltages function to over-drive the gate terminals of the first pair of transistors, thereby increasing the amount of current passed there through. A memory device comprising the multiplexer circuit and method for operating the multiplexer circuit are also provided herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.