Method and apparatus for decreasing layout area in a pipelined analog-to-digital converter
US7471227B2 · kind B2 · utility
3Cited by
4References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2006 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Aug 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In accordance with one embodiment, there is provided a pipelined analog-to-digital converter (ADC) device. The pipelined ADC includes a first stage and a second stage. The first and second stages are configured to share a sub-ADC and a sub-digital-to-analog converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.