High current interconnect structure for IC memory device programming
US7471539B2 · kind B2 · utility
14Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2005 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Jan 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
Abstract
A method and system for a high current semiconductor memory cell provides a semiconductor memory cell with two current carrying structures. At least one of the current carrying structures is segmented and formed of narrow wire segments from one or more levels coupled to wider connective squares of another level. The wire segments may be a conductive material and the connective squares a refractory material. The short length wire segments may include a length less than the average grain size of the material of which they are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.