Non-volatile semiconductor memory based on enhanced gate oxide breakdown
US7471540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2007 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Jan 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate oxide break down can be controlled to achieve the best memory programming results. The conductivity of the programmed memory cell is increased greatly and conductivity variation between the memory cells is reduced. This is achieved by adding a body bias during the programming process. The body here refers to a P-well formed within the deep N-Well. Furthermore, the read voltage offset is reduced greatly with this new memory configuration. These improved programming results will allow faster read speed and lower read voltage. This new structure also reduces current leakage from a memory array during programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.