Patent · US Active

Dual port random-access-memory circuitry

US7471588B2 · kind B2 · utility

7Cited by

7References

13Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Haiming Yu · San Jose, US
Tony Ngai · Campbell, US
Kok Heng Choe · Bukit Mertajam, MY

Key dates

Filing date	Aug 18, 2006
Grant date	Dec 30, 2008
Priority date	—
Expiry date	Aug 18, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/18
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator transistors and feedback paths. When a write operation is performed on one port of the dual port memory array while a read operation is being performed on the other port of the dual port memory array, the bit line voltage clamping circuitry prevents the voltages on the read port bit lines from dropping too low. This allows the write operation to be performed rapidly, even if the memory cell being written to has been adversely affected by variations due to process, voltage, and temperature.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.