Reconfigurable processing node including first and second processor cores
US7472224B1 · kind B1 · utility
9Cited by
15References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2004 |
| Grant date | Dec 30, 2008 |
| Priority date | — |
| Expiry date | Jan 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/079
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processing node includes a first processor core and a second processor core. The first processor core includes a first cache memory, such as an L2 cache, for example. The second processor core includes a second cache memory, such as an L2 cache memory. The processing node further includes a configuration unit that is coupled to the first processor core and the second processor core. The configuration unit may selectably disable portions of the first and the second cache memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.