Memory-module manufacturing method with memory-chip burn-in and full functional testing delayed until module burn-in
US7473568B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2006 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Aug 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Reliable memory modules are assembled from partially-tested memory chips that are neither individually burned-in nor fully tested. Instead, individual memory chips are partially tested to screen out gross failures and then assembled into memory modules that are inserted into memory-module burn-in boards and placed into a burn-in oven. The memory modules are stressed during burn-in by high temperatures and applied voltages. After burn-in, the memory modules are removed from the memory-module burn-in boards and extensively tested. Functional tests include many test patterns to test all memory locations in the partially-tested memory chips on the memory modules. Tests are performed at corner conditions such as high temperature and voltage. Infant mortality and single-bit faults are detected by the functional tests after module burn-in. The number of insertions into burn-in boards is reduced by the number of memory chips per module minus one, so handling and test costs are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.