Method for forming a shielded gate trench FET with the shield and gate electrodes being connected together
US7473603B2 · kind B2 · utility
25Cited by
326References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2007 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Nov 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A method of forming a field effect transistor includes the following steps. A trench is formed in a semiconductor region, and a shield dielectric layer lining lower sidewalls and a bottom surface of the trench is formed. A shield electrode is formed in a lower portion of the trench, and a dielectric layer is formed along upper trench sidewalls and over the shield electrode. A gate electrode is formed in the trench over the shield electrode, and an interconnect layer connecting the gate electrode and the shield electrode is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.