Method for making integrated circuit chip having carbon nanotube composite interconnection vias

US7473633B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Toshiharu Furukawa · South Burlington, US
• Mark C. Hakey · Saint Albans, US
• David V. Horak · South Burlington, US
• Charles W. Koburger, III · Delmar, US
• Mark E. Masters · South Burlington, US
• Peter H. Mitchell · Jericho, US
• Stanislav Polonsky · Putnam Valley, US

Key dates

• Filing date: Jul 20, 2006
• Grant date: Jan 6, 2009
• Expiry date: Dec 19, 2026

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/842
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.