High density contact to relaxed geometry layers
US7474000B2 · kind B2 · utility
122Cited by
7References
46Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2003 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Dec 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides for a via and staggered routing level structure. Vertically overlapping vias connect to two or more routing levels formed at different heights. The routing levels are either both formed above or both formed below the vias, and all are formed above a semiconductor substrate wafer. In this way vias can be formed having a pitch smaller than the pitch of either the first routing level or the second routing level, saving space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.