Method of producing and operating a low power junction field effect transistor
US7474125B2 · kind B2 · utility
4Cited by
4References
16Claims
0Family size
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Inventor
Key dates
| Filing date | Dec 7, 2006 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Dec 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.