Use of multiple voltage controlled delay lines for precise alignment and duty cycle control of the data output of a DDR memory device
US7474136B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 2007 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Jul 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DLL circuit uses a rising edge DLL to align the rising edge of the output data to the system clock and a falling edge DLL to align the falling edge of the output data. The DLL circuit does not use the falling edge of the input clock to provide a reference for the falling edge DLL. The DLL circuit uses the rising edge of a first reference clock (a buffered version of the input clock) to align the rising edge of the output data. An additional DLL is used to generate a precise second reference clock that is delayed by exactly one-half period of the first reference clock to align the falling edge of the output data. Any variation in the duty cycle of the input clock or the input clock buffer does not effect the duty cycle of the output data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.