Silicon carrier including an integrated heater for die rework and wafer probe
US7474540B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2008 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Jan 10, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4913
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicon carrier package includes a multi-layer member having at least a first layer and a second layer. A first electronic component includes a plurality of connector members that establish a first bond electrically interconnecting the first electronic component to the multi-layer member. A second electronic component includes a plurality of connector members that establish a second bond electrically interconnecting the second electronic component to the multi-layer member. At least one heating element is integrated into one of the first and second layers of the multi-layer member. The at least one heating element is selectively activated to loosen only one of the first and second bonds to facilitate removal of only one of the first and second electronic components from the multi-layer member. The other of the first and second bonds remains intact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.