Bit-line equalizer, semiconductor memory device including the same, and method for manufacturing bit-line equalizer
US7474549B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2007 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Jul 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit-line equalizer, a semiconductor memory device including the bit-line equalizer, and a method for manufacturing the bit-line equalizer, in which the bit-line equalizer includes: first and second polysilicon gates formed in a first direction in proximity to each other, the first and second polysilicon gates having a predetermined distance between them; and a plurality of equalizing transistors formed in a second direction along the first and second polysilicon gates, the equalizing transistors equalizing bit-line pairs, with the equalizing transistors being alternately formed in proximity to the first and second polysilicon gates. The bit-line equalizer can vary the widths of the equalizing transistors irrespective of a memory cell pitch in order to improve an equalizing time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.