Dynamic RAM-and semiconductor device
US7474550B2 · kind B2 · utility
16Cited by
12References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2007 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Apr 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes a plurality of first regions arranged along a first direction, each of which corresponds to a memory array including a plurality of word lines, bit lines and memory cells. A plurality of second regions are provided each of which is arranged alternately with respect to each of the first regions, and each including sense amplifiers connected to said bit lines to form an open line type semiconductor memory. A third region is also provided that is a region not sandwiched by the second regions, wherein the third region includes a plurality of dummy bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.