Parallel test mode for multi-core processors
US7475309B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Feb 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318563
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An embodiment of the present invention is a technique to provide a parallel test mode for multi-core processors. A test access port (TAP) in a first processor core generates a first test data output (TDO) from a first test data input (TDI) or a first delayed TDI according to a TDO select bit. The first delayed TDI is clocked by a test clock (TCK). The first processor core has a first core circuit. The TAP generates a phase select word. A clock generator generates a clock signal synchronized with the TCK and has a low phase and a high phase. A first enable circuit enables first core data from the first core circuit in one of the low and high phases of the clock signal according to the phase select word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.