Systems and methods for diagnosing rate dependent errors using LBIST
US7475311B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2005 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Dec 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems and methods for performing logic built-in self-tests (LBISTs) to detect “at-speed” errors in a digital circuit. In one embodiment, an input bit pattern is propagated through target logic of the digital circuit and captured in scan chains at a normal operating speed to produce a first output bit pattern. This is repeated with the first input bit pattern at a lower test speed to produce a second output bit pattern. Differences between the first and second output bit patterns are then detected to determine whether operation of the digital circuit at the normal operating speed causes errors that are not generated at the lower test speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.