Mechanism for read-only memory built-in self-test
US7475314B2 · kind B2 · utility
7Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2006 |
| Grant date | Jan 6, 2009 |
| Priority date | — |
| Expiry date | Jun 21, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method for on-die read only memory (ROM) built-in self-test (BIST) is disclosed. The method comprises testing odd word line entries of a read-only memory (ROM) array by performing two passes through the ROM array to test each odd word line entry for static and delay faults, testing even word line entries of the ROM array by performing two passes through the ROM array to test each even word line entry for static and delay faults, and testing each entry of the ROM array for static faults masked by dynamic faults by performing two passes through the ROM array. Other embodiments are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.