Methods for forming shielded gate field effect transistors
US7476589B2 · kind B2 · utility
45Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2006 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Dec 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field effect transistor is formed as follows. A trench is formed in a semiconductor region. A dielectric layer lining the trench sidewalls and bottom is formed. The trench is filled with a conductive material. The conductive material is recessed into the trench to thereby form a shield electrode in a bottom portion of the trench. The recessing of the conductive material includes isotropic etching of the conductive material. An inter-electrode dielectric (IED) is formed over the recessed shield electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.