Patent · US Active

Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop

US7477071B2 · kind B2 · utility

0Cited by

14References

20Claims

0Family size

Assignee

Actel Corporation · US

Inventors

Alan B. Reynolds · Long Valley, US
Andrew W. Reynolds · Vastern, GB
Volker Hecht · Barsinghausen, DE

Key dates

Filing date	Mar 11, 2008
Grant date	Jan 13, 2009
Priority date	—
Expiry date	Mar 11, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17728
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.