CMOS output driver using floating wells to prevent leakage current
US7477075B2 · kind B2 · utility
7Cited by
11References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 5, 2006 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | May 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An I/O buffer circuit including: a driver circuit containing a pull-up device in a first floating well and a pull-down device in a second floating well; a first and second biasing circuits to bias the first and second floating wells in response to voltages internal and external to the I/O buffer circuit; and a first and second tracking circuits to bias each of said pull-up and pull-down devices in response to voltages internal and external to the I/O buffer circuit in a shutdown mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.