Structure for the main oscillator of a counter-controlled delay line
US7477112B1 · kind B1 · utility
6Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2006 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Oct 31, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00247
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A counter-controlled delay line includes a main oscillator for delaying edges of an input signal to generate a main clock signal. The main oscillator includes a plurality of gated delay elements connected in a ring. Each gated delay element includes a first control terminal to receive a corresponding load signal, and includes a second control terminal to receive a release signal. The release signal may simultaneously enable and disable state transitions in all delay elements, and the load signals may simultaneously drive an output of each delay element to any selected logic state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.