Methods and systems for determining overlay error based on target image symmetry
US7477396B2 · kind B2 · utility
10Cited by
16References
14Claims
0Family size
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Key dates
| Filing date | Feb 22, 2006 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Feb 18, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70633
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In systems and methods measure overlay error in semiconductor device manufacturing based on target image asymmetry. As a result, the advantages of using very small in-chip targets can be achieved, while their disadvantages are reduced or eliminated. Methods for determining overlay error based on measured asymmetry can be used with existing measurement tools and systems. These methods allow for improved manufacturing of semiconductor devices and similar devices formed from layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.