Processor with scheduler architecture supporting multiple distinct scheduling algorithms
US7477636B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2003 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Jun 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5679
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A processor includes a scheduler operative to schedule data blocks for transmission from a plurality of queues or other transmission elements, utilizing at least a first table and a second table. The first table may comprise at least first and second first-in first-out (FIFO) lists of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a first scheduling algorithm, such as a weighted fair queuing scheduling algorithm. The scheduler maintains a first table pointer identifying at least one of the first and second lists of the first table as having priority over the other of the first and second lists of the first table. The second table includes a plurality of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a second scheduling algorithm, such as a constant bit rate or variable bit rate scheduling algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.