Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
US7478276B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2005 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | Sep 14, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemented to recover from soft errors in logic. The processor is able to dispatch fixed point unit (FXU), load/store unit (LSU), and floating point unit (FPU) or vector multimedia extension (VMX) instructions on the same cycle. Store data is written to a store queue when a store instruction finishes executing. The data is held in the store queue until the store instruction is checkpointed, at which point it can be released to the coherently shared level 2 (L2) cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.