Error-correction memory architecture for testing production
US7478308B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2007 |
| Grant date | Jan 13, 2009 |
| Priority date | — |
| Expiry date | May 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a first circuit that generates error-correction (EC) bits based on received data bits. Memory includes M data portions that store the data bits, where M is an integer greater than one, and M error-correction (EC) portions that store the EC bits. An input receives test data bits. A switching device selectively outputs one of the test data bits from the input and the EC and data bits from the first circuit to one of the M data portions and a corresponding one of the M EC portions. Vector pairs of the test data bits are stored in the memory. Bit values of an nth one of the vector pairs alternate every n bits. Vectors in the vector pairs are shifted n bits relative to each other, where n is an integer greater than zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.