Method and apparatus to reduce latency and improve throughput of input/output data in a processor
US7480747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2005 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Feb 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatus and method having a register circuit to receive a first portion of a packet from an input/output device, cache memory circuit to receive a second portion of the package, and a processing unit to process at least one of the first and second portions of the packet based on instructions in the processing unit. The processing unit and the register circuit reside on a processor. The first portion of the packet is placed into the register circuit of the processor, bypassing a memory device coupled to the processor. The second portion of the packet is placed into the cache memory circuit of the processor, bypassing the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.