Method of designing a semiconductor integrated circuit
US7480875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2005 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Mar 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power supply, an areal demerit can be reduced by reducing a necessary capacitance component as a whole while considering a cell activation rate in the circuit or by selecting the capacitance required to supplement only temporal portions whose power-supply fluctuation is wide after the estimation of a cell operating timing. Also, the process can be conducted in a short time at the early stage of design by using a wiring load model at the time of capacitance estimate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.