Methods and apparatus for Boolean equivalency checking in the presence of voting logic
US7480877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2006 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Feb 26, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31835
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a first aspect, a first method of designing a circuit is provided. The first method includes the steps of (1) providing a model of an original circuit design including a latch; (2) providing a model of a modified version of the original circuit design, wherein the modified version of the original circuit design includes a set of latches associated with the latch of the original circuit design and voting logic having inputs coupled to respective outputs of latches in the latch set; and (3) during Boolean equivalency checking (BEC), injecting an error on at most a largest minority of the inputs of the voting logic to test the voting logic function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.