Junction leakage reduction in SiGe process by implantation
US7482211B2 · kind B2 · utility
10Cited by
1References
19Claims
0Family size
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Key dates
| Filing date | Sep 19, 2006 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Jan 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode on the gate dielectric, forming a stressor in the semiconductor substrate adjacent an edge of the gate electrode, and implanting an impurity after the step of forming the stressor. The impurity is preferably selected from the group consisting essentially of group IV elements, inert elements, and combinations thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.