Through chip connection
US7482272B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Jan 10, 2006 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Mar 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S2301/176
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an electrically conductive path through a portion of a semiconductor material, wherein the semiconductor material abuts a substrate and wherein the semiconductor material comprises multiple electronic devices, involves forming an annular trench in the portion, forming an island of semiconductor material within the annular trench, filling the annular trench with an electrically insulating material, removing at least some of the island of semiconductor material to create an exposed inner surface, metalizing at least a portion of the exposed inner surface with a material, and thinning an outer surface side of the substrate until at least the material from the metalizing is exposed on the outer surface side of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.