Semiconductor circuit arrangement

US7482663B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Gerhard Knoblinger · Villach, AT
• Klaus von Arnim · Munich, DE

Key dates

• Filing date: Jan 16, 2007
• Grant date: Jan 27, 2009
• Expiry date: Feb 21, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

A semiconductor circuit arrangement includes at least one first and a second field effect transistor, where the field effect respectively have at least two active regions with, respectively, a source region, a drain region and an intermediate channel region, the surface of the channel regions having a gate formed on it, insulated by a gate dielectric, for actuating the channeel regions. At least one active region of the second field effect transistor is arranged between the at least two active regions of the first field effect transistor, which results in a reduced mismatch between the two transistors, caused by temperature and local distances.