Store performance in strongly-ordered microprocessor architecture
US7484045B2 · kind B2 · utility
1Cited by
15References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2004 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Jun 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A store operation architecture in which store operation latency and read-for-ownership (RFO) throughput are improved. Embodiments of the invention relate to a method and apparatus to improve store performance in a microprocessor by allowing out-of-order issuance of RFO operations and more efficiently using the store buffer latency periods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.