Deep Buch
20Patents
6h-index
40Co-inventors
69Inventor score
Filing activity: Jun 30, 1998 → Dec 26, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6901522B2 | System and method for reducing power consumption in multiprocessor system | Emerging Cross-Sectional Technologies | 75 | Expired |
| US6772241B1 | Selective interrupt delivery to multiple processors having independent operating systems | Emerging Cross-Sectional Technologies | 19 | Expired |
| US7159220B2 | Flexible acceleration of java thread synchronization on multiprocessor computers | Physics | 14 | Expired |
| US6976099B2 | Selective interrupt delivery to multiple processors having independent operating systems | Emerging Cross-Sectional Technologies | 10 | Expired |
| US7080376B2 | High performance synchronization of accesses by threads to shared resources | Physics | 9 | Expired |
| US6369813B2 | Processing polygon meshes using mesh pool window | Physics | 7 | Expired |
| US7114011B2 | Multiprocessor-scalable streaming data server arrangement | Physics | 6 | Expired |
| US6748512B2 | Method and apparatus for mapping address space of integrated programmable devices within host system memory | Physics | 6 | Expired |
| US9612930B2 | Providing autonomous self-testing of a processor | Physics | 5 | Active |
| US7979699B2 | Processing capacity on demand | Physics | 4 | Active |
| US7694161B2 | Uncore thermal management | Physics | 4 | Active |
| US8122308B2 | Securely clearing an error indicator | Physics | 4 | Active |
| US7506339B2 | High performance synchronization of accesses by threads to shared resources | Physics | 2 | Active |
| US8700937B2 | Uncore thermal management | Physics | 1 | Active |
| US7484045B2 | Store performance in strongly-ordered microprocessor architecture | Physics | 1 | Expired |
| US9690640B2 | Recovery from multiple data errors | Physics | 1 | Active |
| US9471118B2 | Uncore thermal management | Physics | 1 | Active |
| US8244985B2 | Store performance in strongly ordered microprocessor architecture | Physics | 0 | Active |
| US9602237B2 | Sideband parity handling | Electricity | 0 | Active |
| US12235720B2 | Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS) | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.