Systems and methods for LBIST testing using isolatable scan chains
US7484153B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 6, 2005 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Mar 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits, where boundary scan chains in functional blocks of the circuits can be selectively coupled/decoupled to isolate the functional blocks during LBIST testing. In one embodiment, processor cores of a multiprocessor chip are isolated and LBIST testing is performed to determine whether any of the processor cores is malfunctioning. If none of the processor cores malfunctions, the processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor is fully functional. If one or more processor cores malfunctions, these processor cores are isolated and the remaining processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor operates properly with reduced functionality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.