Clock-gating through data independent logic
US7484187B2 · kind B2 · utility
7Cited by
10References
5Claims
0Family size
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Key dates
| Filing date | Dec 7, 2005 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Sep 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Given a function F of a circuit having a data latching device and a feedback loop feeding an output Q of the device into logic which feeds the device, a method includes extracting at least one data independent case and clock-gating the device with the at least one data independent case. The method also includes eliminating the feedback loop if function F depends only on Q with a positive polarity or leaving the feedback loop if function F depends on Q in both positive and negative polarities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.