Method for asynchronous clock modeling in an integrated circuit simulation
US7484196B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2006 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Apr 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms for asynchronous clock modeling in an integrated circuit simulation are provided. The mechanisms of the illustrative embodiments provide clock skewing logic for phase shifting a clock signal in an integrated circuit design. This clock skewing logic adds delay to one or more clocks of an integrated circuit design to thereby place that clock out of phase with other clocks in the integrated circuit design. In one illustrative embodiment, delay is introduced into a clock net in an increasing manner with each enablement of the clock skewing logic. In another illustrative embodiment, the introduced delay is increased and decreased within a window from no phase shift of the clock net up to a maximum phase shift of the clock net. Once the maximum phase shift is reached, the amount of delay introduced is decreased with subsequent enablement of the clock skewing logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.