Semiconductor package having step type die and method for manufacturing the same
US7485955B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2005 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Mar 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A variety of non-rectangular IC chips having a stepped or modified periphery or edge profile including one or more recessed or indented peripheral regions are provided for incorporation in modified package configurations, single chip packages and multi-chip assemblies, both stacked and/or planar. In the planar configurations, the recessed regions may be utilized, in cooperation with another appropriately sized IC chip, to increase the packing density of the resulting device. Similarly, in the stacked configuration, the recessed regions may be utilized to provide access to bond pads of lower chips and thereby reduce the need for spacers or peripheral thinning techniques and thereby improve the strength of the resulting assembly and/or reduce the overall height of the stacked structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.