Integrated circuit testing method using well bias modification

US7486098B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Anne Elizabeth Gattiker · Austin, US
• David A. Grosch · Burlington, US
• Marc D. Knox · Mechanicsville, US
• Franco Motika · Hopewell Junction, US
• Phil Nigh · Williston, US
• Jody Van Horn · Underhill, US
• Paul S. Zuchowski · Williston, US

Key dates

• Filing date: Oct 22, 2007
• Grant date: Feb 3, 2009
• Expiry date: Oct 22, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/275
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The method improves the resolution of IDDQ testing and diagnosis by modifying well bias during testing. The method applies to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the method relies on using the well bias to change transistor threshold voltages.