Integrated circuit with graduated on-die termination
US7486104B2 · kind B2 · utility
29Cited by
22References
90Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2006 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Jun 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017545
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device having graduated on-die termination. The integrated circuit device includes an input to receive a data signal, and first and second termination circuits. The first termination circuit includes a first load element and a first switch element to switchably couple the first load element to the data signal input. The second termination circuit includes a second load element and a second switch element to switchably couple the second load element to the data signal input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.