DDR interface for reducing SSO/SSI noise
US7486702B1 · kind B1 · utility
19Cited by
8References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 11, 2003 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Jan 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved DDR interface uses single-ended technology and phase-shifts all output data signals and the output source clock signal so that each output signal switches at a different time so that IDDQ spikes caused by I/O switching do not accumulate. A dynamic phase adjustment circuit on the receiver compensates for the phase differences. Clock jitter and skew is reduced and the number of IDDQ pins is reduced to provide a more effective design and high density package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.