Prioritized bus request scheduling mechanism for processing devices
US7487305B2 · kind B2 · utility
48Cited by
18References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 7, 2006 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Nov 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.