Managing write-to-read turnarounds in an early read after write memory system
US7487318B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2007 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Sep 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1647
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.