Method for increasing manufacturability of a circuit layout
US7487492B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2006 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | May 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one exemplary embodiment, a method for increasing manufacturability of a circuit layer includes determining a threshold value for at least one image property from a repetitive section of the circuit layout. According to this embodiment, the method further includes performing a simulated lithographic process using the circuit layout to determine a number of simulated values of the at least one image property for a non-repetitive section of the circuit layout. The method further includes comparing each of the simulated values with the threshold value to determine printability of the non-repetitive section of the circuit layout prior to lithographically printing the circuit layout on a wafer. The method further includes modifying the non-repetitive section of the circuit layout if the threshold value is greater than at least one of the simulated values. By modifying the non-repetitive section of the circuit layout, manufacturability of the circuit layout can be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.