Method for forming stacked via-holes in printed circuit boards
US7488428B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2006 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | Oct 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/108
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for forming stacked via-holes on a printed circuit board includes the steps of: providing a printed circuit board having a conductive trace formed on a side surface thereof; forming a first copper-clad laminate on the side surface having the conductive trace; forming a number of first copper micro-via in a copper layer of the first copper-clad laminate; forming a second copper-clad laminate on the surface of the copper layer having the first copper micro-via of the first copper-clad laminate; forming a number of second copper micro-via in a copper layer of the second copper-clad laminate by a first laser on the basis of the first copper micro-via, each second copper micro-via being located corresponding to its correspondingly first copper micro-via; and removing corresponding resin layer portions of the first and second copper-clad laminates, using a second laser, to yield the respective stacked via-holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.