NAND flash memory cell array with adaptive memory state partitioning
US7489548B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2006 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | Dec 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND type flash memory is organized into NAND strings with each being a chain of memory cells in series and connected via select transistors on both ends of the string to either a bit line or a source line. The memory cells adjacent both ends of a NAND string are particularly susceptible to errors due to program disturb. An adaptive memory-state partitioning scheme is employed to overcome the errors, in which each memory cells are generally partitioned to store multiple bits of data, except for the ones adjacent both ends where relatively less bits are stored. In this way, the storage of relatively less bits in the memory cells adjacent both ends of a NAND string affords sufficient margin to overcome the errors. For example, in a memory designed to store 2-bit data, the cells adjacent both ends of a NAND string would each be configured to store one bit of the 2-bit data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.