High speed adder design for a multiply-add based floating point unit
US7490119B2 · kind B2 · utility
3Cited by
5References
21Claims
0Family size
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Key dates
| Filing date | Dec 11, 2003 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | Oct 26, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and computer program product are provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.